The present invention relates generally to electronic circuits and, more particularly, to a method and apparatus for analog-to-digital pipeline conversion.
An N-bit algorithmic analog-to-digital (A/D) converter, either a pipeline or cyclic converter, generally includes a predetermined number J of conversion stages, each conversion stage being a K-bit stage, where Jxc3x97K=N.
FIG. 1 is a block diagram illustrating a prior art conversion stage of a pipeline analog-to-digital (A/D) converter. As illustrated in FIG. 1, the conversion stage 100 includes a sample/hold S/H module 110 to receive an analog input voltage VRESixe2x88x921 105, a K-bit A/D subconverter module ADSC 120 coupled to an output of the S/H module 110 to estimate the analog input voltage VRESixe2x88x921 105 into a digital signal 125 by extracting a predetermined number K of bits from the VRESixe2x88x921 105, and a K-bit digital-to-analog (D/A) converter DAC 130 coupled to the ADSC 120 to receive the K-bit signal 125 from the ADSC 120 and to create an analog estimate VDACi 135 of the input voltage VRESixe2x88x921 105. A summing circuit 140 coupled to the S/H module 110 and to the DAC 130 subsequently subtracts the analog estimate VDACi 135 from the analog input voltage VRESixe2x88x921 105 and transmits the resulting analog residue voltage 145 to an amplifier module AV 150. The AV 150 amplifies the residue voltage 145 by a 2K factor to obtain an amplified residue voltage VRESi 155 and transmits the voltage VRESi 155 to a subsequent conversion stage (not shown) of the A/D converter. The amplified residue voltage 155 can be calculated with the formula
VRESi=2Kxc3x97VRESixe2x88x921xe2x88x92VDACi
In any algorithmic A/D converter, the overall linearity of the converter is generally determined by the linearity of the DAC 130 of each conversion stage 100. Thus, a solution designed especially for high linearity and high speed applications uses K=1 and a 1-bit ADSC 120 and DAC 130. With a single-bit decision, there is always a straight line that can be drawn between the positive and negative reference voltages. In this case, the ideal gain of the conversion stage 100 is 2 and the residue equation becomes
VRESi=2xc3x97VRESixe2x88x921xe2x88x92VDACi
FIG. 2 is a schematic diagram illustrating a prior art analog residue computation circuit. As illustrated in FIG. 2, the circuit 200 combines the S/H module 110, the ADSC 120, the DAC 130, and the summing circuit 140 shown in the conversion stage of FIG. 1 into a single switched capacitor circuit 200.
During a first phase of a non-overlapping clock, known as the sample phase, a switch S1C 222 holds operational amplifier 223 as a voltage follower and the analog input voltage VRESixe2x88x921 105 minus the offset of the operational amplifier 223 is sampled on both capacitors 211 and 212 through switches S1A 201 and S1B 202, respectively.
During a second phase of the non-overlapping clock, known as the hold phase, the bottom plate of the capacitor 211 is coupled to the output of the operational amplifier 223 through switch S2B 221 and the bottom plate of the capacitor 212 is coupled to Dixc3x97VREF through switch S2A 203, where the data Di is the data input and can take one of two values, xe2x88x921 or +1, at any given pipeline stage.
The speed of the pipeline A/D converter is determined by the speed of a single conversion stage 100 illustrated in FIG. 1. The alternating conversion stages 100 of the converter work on alternating phases of the clock, such that, in any phase, half of the conversion stages 100 are in the hold phase and half are in the sample phase. Thus, for correct functionality, the sample phase of one conversion stage 100 must end after the residue voltage transmitted from the previous conversion stage 100 (in hold phase), for example, the analog residue voltage VRESixe2x88x921 105 in FIG. 1, has settled to its final value. Otherwise, for example, if the conversion clock is too fast, the residue value transferred to the next conversion stage 100 will be incorrect. As a result, high speed converters require conversion stages 100 with fast settling times.
For switched capacitor implementations, such as the circuit 200 illustrated in FIG. 2, assuming a single dominant-pole operational amplifier 223, the settling time to within N bits of accuracy is determined by the formula
TS=Nxc3x97ln(2)xc3x97CL/xcex2xc3x97gM
where gM/CL is the dominant pole of the operational amplifier 223 and xcex2 is the feedback factor (feedback gain). Thus, for high speed converters having small feedback factor xcex2, what is needed is a method and apparatus that minimizes the settling time.
Another perceived limitation of the high speed pipeline A/D converters is the comparator ADSC 120 decision time. FIG. 3 is a timing diagram illustrating the timing of two consecutive prior art conversion stages of a pipeline A/D converter. As shown in FIG. 3, after the end of the sample phase, the conversion stage 100 has to execute first a compare phase. The settling phase of the operational amplifier 223 cannot start before the completion of the compare phase because there is no information about the region of the residue voltage conversion. On the other hand, the compare phase has to have a correct input; therefore it has to wait for the previous conversion stage to settle. Thus, what is needed is a method and apparatus in which the comparator decision time is not a major limitation on the conversion clock at high speeds.
A method and apparatus for analog-to-digital pipeline conversion are described. The apparatus includes a sample/hold circuit having an input to receive an analog input voltage, a comparator device coupled to the input of the sample/hold circuit to receive the analog input voltage, and a separate gain circuit coupled to an output of the sample/hold circuit and to the comparator device. The sample/hold circuit and the comparator device sample the analog input voltage and the separate gain circuit amplifies an analog residue voltage obtained from the analog input voltage to obtain an amplified analog residue voltage in a first phase of a non-overlapping clock. The analog residue voltage is obtained in a second phase of the non-overlapping clock, when the sample/hold circuit holds the analog input voltage sampled in the first phase, and the comparator device compares the analog input voltage sampled in the first phase with a reference voltage value.
Other features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description, which follows below.